The HDLBits site has a great set of Verilog “exams” that would be ... from the silly (output a constant 1 or 0) to full-blown state machines and testbenches. The site isn’t tutorial in ...

Finite state machines (FSMs) have finite number of states ... PSL statements can be embedded in code written in either Verilog or VHDL, since there are flavors of PSL for both languages. However, the ...