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Springer 2010. [2] IC Latch-Up Test JESD78E, JEDEC Solid State Technology Association, 2016. [3] ISO 10605 Standard, 2008-07-15, ISO, Switzerland. [4] ANSI/ESD SP 5.6-2009, “Electrostatic Discharge ...
A topology-aware flow applies external latch-up design rules, while a voltage-aware flow applies mixed-voltage latch-up design rules across all levels of a 2.5/3D IC layout. These flows are based on ...
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