If it doesn't locate it in the L1 cache, it proceeds to the L2 cache, and then the L3 cache. If the CPU finds the requisite data in any of the three caches, this is termed a cache hit.

The L in L1, L2, and L3 stands for "Level", hinting at their hierarchical structure. The L1 cache is the fastest of the lot, with bandwidth close to 1TB/second and just 1 nanosecond of latency.

Recently, IBM debuted its Telum microprocessor with an interesting and unusual cache structure. Telum has the usual L1 and L2, but instead of a physical L3, the CPU deploys a virtual L3.

L2 cache is a bit slower to access than the L1 cache, but the trade off is that it is much, much larger—on the order of an entire megabyte on Zen 4 and a full two megabytes on Raptor Cove.

CPUs have a number of caching levels. We've discussed cache structures generally, in our L1 & L2 explainer, but we haven't spent as much time discussing how an L3 works or how it's different ...