Jin-Woo Han is senior scientist at NASA’s Ames Research Center in California’s Silicon Valley. Along with colleagues Meyya Meyyappan, Myeong-Lok Seol and Jungsik Kim, he has designed a nanoscale ...

Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware. Science Advances, 2021; 7 (32): eabg8836 DOI: 10.1126/sciadv.abg8836 ...

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is ...

Dubbed BiCOM-III, TI's recently announced silicon-germanium (SiGe) complementary bipolar-CMOS manufacturing process integrates both NPN- and PNP-type bi-polar transistors. The result of this first ...